The Development of a Preprocessing Circuit Using Clocked CMOS Neuron Inverters for a Retinal Prosthesis System

In implantable electronic medical devices, low power consumption and small size are important requirements to design efficient implantable circuits. As a preprocessing circuit of the retinal prosthesis system, this paper presents two types of image processing circuits: a CMOS median filter and a CMOS binarizing circuit. Owing to the CMOS circuit design utilizing clocked neuron CMOS inverters, the proposed circuits can achieve median filtering and binarizing of the captured image without arithmetic logic circuits. Furthermore, the through-current of neuron CMOS inverters can be suppressed by adjusting the duty cycle of clock pulses. Therefore, the proposed circuits achieve not only simple circuit configuration but also low power consumption. The results of the simulation program with integrated circuit emphasis (SPICE) simulation demonstrate the effectiveness of the proposed circuits.


Introduction
In the field of biomedical engineering, the demand of implantable electronic medical devices is growing rapidly.Among others, the development of a retinal prosthesis system (1)(2)(3) is one of the most challenging issues to support partial or total blind patients.In the retinal prosthesis system, an image data captured by an external camera is transmitted to an IC chip implanted near retina by wireless (2,3) .Hence, the retinal prosthesis system consists of a camera, signalprocessing units, a wireless transmitter & receiver, and an implanted stimulator IC chip.However, the existing retinal prosthesis system is bulky and not power-efficient.To develop an efficient retinal prosthesis system with small size and low power consumption, firstly, we focused on the preprocessing circuit to perform median filtering, resizing, and binarizing of the input image.
In previous studies, many types of the preprocessing circuits have been proposed.For example, Kalali et al. implemented an adaptive median filter into a Field Programmable Gate Array (FPGA) chip (4) .Due to the low complexity 2D adaptive median filter algorithm, low power consumption can be realized by Kalali's circuit.In this way, the efficient preprocessing circuit can be realized easily by utilizing embedded systems such as FPGA, Intel Edison, Aduino, and so on.However, the hardware approach based on the embedded system is too bulky for the retinal prosthesis system.Different from these approaches based on embedded systems, Lee et al. proposed a bit-level scalable median filter (5) .The bit-level scalable median filter is suitable for IC implementation, because it can be designed by CMOS technology.Following this, Yamasaki et al. suggested a high speed median filter using floating-gate-MOS-based low-power majority voting circuits (6) .Due to the floating gate MOS technology, the median filter proposed by Yamasaki et al. can achieve not only low power consumption but also high speed operation.The floating gate MOSFET is referred to as a neuron MOSFET (7 -10) .It is known that the floating gate MOS technology can achieve high-speed operation, small size, and low power consumption (6 -10) .However, in order to realize more efficient implantable circuit, there is still room for improvement in the point of power consumption.
In this paper, we propose a novel preprocessing circuits using clocked CMOS neuron inverters: CMOS median filter and CMOS binarizing circuit.Owing to the CMOS circuit design utilizing clocked neuron CMOS inverters, the proposed circuits can achieve median filtering and binarizing of the captured image without arithmetic logic circuits, such as adder, subtractor, multiplier, and divider.Furthermore, the through-current of neuron CMOS inverters can be suppressed by adjusting the duty cycle of clock pulses.Therefore, the proposed circuits achieve not only simple circuit configuration but also low power consumption.To clarify the characteristics of the proposed circuits, SPICE (simulation program with integrated circuit emphasis) simulations are performed.
The rest of this paper is organized as follows.In section 2, the proposed CMOS median filter is described.Next, in section 3, the proposed binarizing circuit is presented.Simulation results are shown in section 5. Finally, conclusion and future work are drawn in section 6.

Operation Principle
The operation principle of the proposed median filter is based on the binary search algorithm.To obtain the k-th (k=0, …, N-1) bit of the median value Mi[k] (i=1, …, m×n) from the input image of m×n pixels, the following operation is performed: where Pj[k] is a value of the j-th pixel and W is the window size.According to the median value Mi[k], the value of the ith pixel Pi[k] is changed as follows: By iterating the operation of ( 1) and ( 2) from k=N-1 to 0, the median value of Pi is derived.

Circuit Configuration
Figure 2 illustrates the block diagram of the proposed CMOS median filter.As you can see from figure 2, the proposed median filter consists of bit-comparators (BCs) and majority circuits (MCs).In figure 2, the median detection is performed by a bit-comparison-based technique in order to realize small hardware cost.
Figure 3 illustrates the logic circuit (LC) in the bitcomparator.The logic circuit of figure 3 is designed to realize the following bit-comparison: and In ( 3)-( 5), Mi[k] is the k-th bit of the median output and Li [k]  is the k-th bit of the BC output.The majority of Li[k] is detected in the majority circuit (MC).In the proposed median filter, the majority circuit is designed by using clocked neuron CMOS inverters.Figure 4 illustrates the proposed majority circuit using a clocked neuron CMOS inverter, where Cp denotes the parasitic capacitance.When the clock Ф is in a high level, the clocked neuron CMOS inverter behaves as a traditional neuron CMOS inverter (8 -10) .In this timing, the floating gate voltage VFi[k] of the clocked neuron inverter is given by where Cu is a unit capacitance between an input terminal and the floating gate, CFN is a capacitance between the floating gate and N-type region, and CFP is a capacitance between the floating gate and P-type region.In the proposed median filter, the unit capacitance Cu is designed to satisfy the following conditions: From (7), the floating gate voltage VFi can be rewritten as where From ( 8) and ( 9), we have As you can see from (10), the clocked neuron inverter behaves as a majority circuit when the clock Ф is in a high level.On the other hand, the clocked neuron inverter becomes high-impedance when the clock Ф is in a low level.In this timing, the output voltage is held in Cp.In other words, the proposed majority circuit behaves like a sample-and-hold circuit.Therefore, by adjusting the duty cycle of the clock pulse, the proposed median filter can reduce power consumption, because the through-current of the neuron inverter is suppressed.

Operation Principle
After the median filtering, the input image is converted to a binary image and is resized to the image of m'×n' pixels.To obtain the pixel value of the resized image, Bi (i=1, …, m' ×n'), from the input image of m×n pixels, the following operation is performed: where W' is the window size to resize the input image.In other words, the resized image satisfies the following conditions:

Circuit Configuration
To achieve small power consumption and small hardware cost, clocked neuron MOSFET's are employed in the design of the proposed binarizing circuit.Figure 5 illustrates the proposed binarizing circuit using a clocked neuron CMOS inverter.In the proposed binarizing circuit, the floating gate capacitance is designed as 2 N-1-k ×Cu for Pi [k].Owing to the binary-weighted floating capacitances, the proposed binarizing circuit requires no arithmetic logic circuit such as adder, multiplier, divider, and so on.Therefore, the proposed circuit can achieve simple circuit configuration.
In figure 5, the floating gate voltage VFBi of the clocked neuron inverter is given by where the unit capacitance Cu satisfies the condition of (7).From ( 7) and (13), we get From ( 14) and (15), we have the pixel value of the resized image as follows: As you can see from ( 16), in spite of a simple circuitry, the proposed circuit can achieve not only binarization but also resizing.Furthermore, owing to the clocked neuron inverter, the proposed circuit can reduce power consumption by adjusting the duty cycle of the clock pulse.

Simulation
To clarify the characteristics of the proposed circuits, SPICE simulations are performed by assuming 0.35μm CMOS process.

CMOS Median Filter
As an example of the proposed median filter, the 3bits/3-inputs proposed circuit was designed.Figure 6 demonstrates the simulated output of the proposed median filter, where the supply voltage is 1.8V and the duty cycle is 0.5.In figure 6, the input voltages, P1, P2, and P3, are as shown in Table 2.As you can see from figure 6 and Table 2, the proposed median filter can derive the median value Mi from P1, P2, and P3. Figure 7 shows the power consumption of the proposed median filter as a function of the duty cycle.In figure 7, the blue-line shows the power consumption of the proposed median filter, the orange-line shows the power consumption of the conventional median filter using floating-gate-MOS-based low-power majority voting circuits (6) , and the grey line shows the conventional median filter using CMOS majority circuits (5) shown in figure 8.As figure 7 shows, the proposed median filter can reduce the power consumption by controlling the duty cycle.Concretely, the proposed median filter reduced power consumption more than 37% from the conventional median filter (6) when the duty cycle is 0.5.Needless to say, the setting of duty cycle depends on the response speed of CMOS transistors.

Binarizing Circuit
As an example of the proposed binarizing circuit using a clocked neuron CMOS inverter, the 4-bits/4-inputs proposed circuit was designed.Figure 9 demonstrates the simulated output of the proposed binarizing circuit, where the supply voltage is 1.8V and the duty cycle is 0.5.In figure 9, the input voltages, P1, P2, P3 and P4, are as shown in Table 3.As you can see from figure 9 and Table 3, the proposed binarizing circuit can offer the pixel value of the resized image, Bi. Figure 10 shows the power consumption of the proposed circuit as a function of the duty cycle.In figure 10, the blue-line shows the power consumption of the proposed circuit with a clocked neuron CMOS inverter.On the other hand, the orange-line shows the power consumption of the proposed circuit without a clocked neuron CMOS inverter.As figure 10 shows, the proposed circuit with a clocked neuron CMOS inverter can reduce the power consumption by controlling the duty cycle.Concretely, more than 43% power consumption was reduced when the duty cycle is 0.5.

Fig. 9 .
Fig. 9. Simulated output of the proposed binarizing circuit with a clocked neuron CMOS inverter.

Table 2 .
Setting of SPICE simulation.

Table 3 .
Setting of SPICE simulation.