A Method for Weight Set Compaction in Power Aware Multiple Weighted Random BIST

This paper presents a multiple weight set weighted random BIST scheme to perform power aware test which takes into account peak power constraint and reducing the number of required weight sets. Exceeding the peak power budget during test provokes problems such as erroneous circuit function due to IR drop and electrical damage to the circuit. However, excessive power reduction during test can degrade fault screening capability of the test since the test environment becomes substantially less stringent than the environment in which the device is actually used. Therefore, controlling power consumption during test operation is important to perform adequate testing. In this paper we address both these problem simultaneously. The main contribution of this paper is to provide an efficient scan based weighted random BIST scheme within power constrain. We assume full scan environment, test per scan testing, and single stuck-at fault model. Genetic algorithm (GA) based optimization method is proposed to find effective weight sets.


Introduction
Power consumption during scan test mode is generally much higher than the power consumed in normal operation because the scan test scheme changes circuit behavior, and the test patterns generated by automatic test pattern generators (ATPG) tend to induce high switching activity (1) .The high power consumption during test mode can provoke many problems such as cooling difficulties of heat dissipation, circuit damage and deterioration of overall product yield.Especially in the current low power designs, low power dissipation during test mode without any test quality degradation is becoming important, and methods have been presented to solve these problems (1) .
As one of the efficient design for testability (DFT) solutions, built-in self test (BIST) scheme is being as a mature approach for VLSI designs that can help avoid the difficulties of external testing.The BIST circuit is embedded in a VLSI chip occupies a small chip area.Main benefit of BIST concept is that testing can be performed under high observable and high controllable environment, because there is no limitation of the number of external pins.In BIST, pseudo-random pattern testing using linear feedback shift register (LFSR) and multiple input signatures register (MISR) are usually exploited since their low impact on hardware overhead is attractive.However, it is well known that often a large number of LFSR generated test patterns are required to get acceptable fault coverage, and yet random pattern resistant (r.p.r.) faults are hard to detect despite applying huge number of test patterns.Furthermore, low correlation between any successive two random test patterns increases power consumption during BIST.Besides, excessive scan test power consumption, such as scan-shift power and capture power during scan test is also becoming a major concern (2) .Several low-power BIST approaches have been proposed to address these problems.In reference (3), weighted random test patterns which were assumed to induce high switching activity were inhibited, and LFSR reseeding method has been proposed.Scan-shift toggle suppression and test pattern suppression techniques have been proposed in reference (4).Low transition test pattern generation method has been proposed in reference (5), and a 3-weight weighted random BIST method and scan-reordering have been proposed in reference (6).Weighted random BIST scheme with special scan cell deign for bit fixing has been proposed in reference (7).In our previous study, we exploited fault clustering using circuit topology to control power consumption (14) .
This paper presents a weight set compaction method in multiple weight set weighted random BIST approach to perform power aware test which considers the constraint of peak power consumption during scan capturing.We assume full scan environment and test per scan testing.Generally, exceeding peak power consumption during test sequence induces many problems, such as erroneous circuit function due to IR drop and electrical damage to the circuits (1), (11) .In many previous research works, they have been focusing on energy and power reduction to as low as possible.This can degrade fault screening capability since the test environment might become less stringent than the actual use environment.Since large number of weight set for weighted random pattern generation would increase the overhead of BIST circuit, the number of required weight sets should be reduced.
The main contribution of our approach is to provide an efficient scan based weighted random BIST scheme within peak power constraint and adequate energy consumption.The major problems of power consumption in scan testing are scan shift power violation and scan capture power violation (11) (13) .The scan shift power can be reduced by insertion of gating logic on scan cells output, reordering scan cells, dividing a scan chain and so on (9), (10), (12) .However, peak power of scan capturing on random BIST scheme is hard to manage, because it depends on consecutive two patterns.Although several approaches had been shown to control peak power consumption (11), (13) , no approaches have been found for multiple weighted random testing.In this paper, we focused on avoiding peak power violation during scan capturing.A weight biasing procedure is performed to restrict the amount of test power consumption.The weights are biased toward 0 or 1 in order to adjust the amount of power consumption.Fundamental idea of this approach is that a weight set looking after larger number of faults might create higher power consumption, and a weight set focusing on small number of faults might create low power consumption.Assuming single stuck-at fault model, genetic algorithm (GA) based optimization method is proposed to find effective weight sets.
The rest of this paper is organized as follows.Section 2 describes power consumption models and concept of power reduction.Section 3 introduces architectures of proposed BIST method.Section 4 describes GA based weight set optimization method.Experimental results for a set of benchmark circuits are presented in Section 5. Finally, conclusion is described in Section 6.

Power Consumption Model and Estimation Metric
Power consumption in typical CMOS technology devices can be classified into static or dynamic.Dynamic power dissipation is caused by switching activity of CMOS transistors.Charging and discharging of load capacitances connecting from the transistors, and instantaneous short circuit during dynamic turning phase of the transistors are the main sources of the dynamic current flow.In recent VLSI designs, dynamic power dissipation is still dominant in standard CMOS devices because dynamic current flow is relatively larger than the static current flow (1) .
As dynamic power consumption model, we use switching activities of gates in CMOS circuits since the switching current contributes to power consumption significantly and reflects actual power consumption well.The weighted switching activity (WSA) is exploited to provide a better estimate of the actual power consumption, which is defined as the number of transitions on a gate output signal multiplied by its capacitance (4) .For simplicity, we used the number of fan-outs of each gate as the amount of the load capacitance.Therefore, the total power consumption is derived from the sum of the WSA of all gates.The factors that are important for evaluating power consumption are: energy, average power, instantaneous power, and peak power.These are defined below (8) .
• Energy.Energy is the total switching activity during test application, and is derived as the sum of WSA applying all test patterns.• Average power.Average power is the total distribution of power over a time period.This is derived from the radio of the energy to the number of required test patterns.Elevation of average power increases the thermal load and might cause of structural damages.
• Instantaneous power.Instantaneous power is the value of power consumption at any given instant.This value is derived from the sum of WSA of each gate by applying consecutive two test patterns.
• Peak power.Peak power is the highest power value at any instant.We define it as the highest instantaneous power consumption during test period, so that it is derived from the highest sum of WSA of each gate by applying consecutive two patterns during scan capturing (13) .

Controlling Power Consumption
Minimizing test length and reducing average power are two common ways to reduce total energy.Generally, there exists a trade-off between the two approaches (8), (10) .Figure 1 shows a rough outline of the power consumption (WSA) during consecutive two test patterns.If test length is minimized without any loss of fault coverage, such as during ATPG test patterns, the average power and peak power will be increased by its high switching activities.The average power could be simply reduced by making test length longer; however, it increases the total energy consumption.Therefore, finding an efficient trade-off point between test length and average power is important to perform effective testing under the power constraints.On the other hand, excessive power reduction of test might be inappropriate for screening faults because the electrical and thermal test environment becomes relatively slack compared to the normal operation of the circuit.Thus, it is important to consider obtaining adequate average power consumption with the restriction of peak power consumption within a design budget for efficient testing.In order to control the amount of power consumption, we propose a weight biasing method.Figure 2 shows a basic outline of the relationship between power consumption and the size of target fault cluster.The fault cluster is defined as a set of target faults for test pattern generation.If the generated test patterns are able to detect many faults, higher switching activities will occur in the circuit under test (CUT).On the contrary, test patterns generated by exploiting strongly biased weight, which target small number of faults will induce small switching activity.Therefore, the approximate amount of power consumption is able to be controlled by handling the size of fault cluster.

Fig. 2. Relationship between power consumption
and fault cluster size.

Proposed Weighted Random BIST Scheme
We assumed full-scan and test per scan architecture in our proposed weighted random BIST scheme.For biasing LFSR generated patterns, we proposed two cases of weight variations: 9 kind of weight (0, 1, 0.5, 0.125, 0.25, 0.75 and 0.875).Figure 3 shows a proposed BIST architecture which is almost as same as conventional weighted random BIST configurations.Thus, we have not discuss about hardware overhead of the BIST circuit.

Weight Sets Computation Algorithm
In order to obtain optimal weight sets for random test pattern generation, we proposed GA based optimization method.Figure 4 shows proposed weight sets computation algorithm.First of all, whole faults excepting redundant faults are divided into two groups by applying equi-probable random patterns.The one is for r.p.r.faults and the other group is easy to detect faults.Weight sets are generated for r.p.r faults group firstly.Redundant fault are eliminated by pre-processed ATPG.
Then, GA based weight set optimization are performed.If the result of the weight set optimization could not pass the constraint of peak power consumption, the weights are biased toward 1 or 0, and optimization will be performed again (Figure 4 (1)).
In the GA based weight set optimization, ATPG test patterns are exploited to take care r.p.r.faults which can be detect only particular test patterns.The ATPG test pattern for the fault is put into the initial population of GA based procedure.This would help to achieve 100% fault efficiency.
Weight sets shifting is performed to reduce the number of weight sets (Figure 4 (2)).In this procedure, after obtaining 4 weight sets, the first weight set is excluded and the rest of 3 weight sets are evaluated by fault simulation.Then a new weight set is derived by weight set optimization procedures and the weight set is appended to the 3 weight sets.Again, the oldest weight set is excluded.This procedure repeats 16 times to get 4 efficient weight sets.After this procedure, The 4 weight sets are fixed and other weights sets are generated for still undetected faults.

Experimental Results
Experiments were performed on a set of ITC'99 benchmark circuits.Before performing the experiments, we obtained ATPG test patterns for each benchmark circuit to eliminate redundant faults and to take care r.p.r faults in the GA based weight sets optimization.The number of backtrack limit in the ATPG was 1,000,000.ATPG aborted faults were not eliminated from target faults.Initially, we applied 131,072(=217) equi-probable random test patterns to determine the amount of the maximum peak power.The amount of target peak power is derived from multiplying "1 -reduction rate" by the maximum peak power.We assumed 0% 10% 20% 30% 40% 50% and 60% peak power reduction rates respectively.In the simulation, weight variation is 9-weight (Fix 0, Fix 1, 0.125, 0.25, 0.5, 0.75 and 0.875).Table 1 shows the result of the experiment.In the table 1, "0% target peak power reduction rate" means that no constraint to peak power dissipation has been applied.The "fault efficiency" in the table was calculated by excepting ATPG undetectable faults, but ATPG aborted faults were included.In case of b14 circuit, aborted faults in ATPG were detected in the optimization process.The "Average Power" represents average power (WAS) of consecutive 2 random patterns.The "Peak Power" represents the maximum peak power (WSA).Almost all circuits satisfy the target peak power reduction rates with archiving high fault coverage.Since the proposed GA based optimization process focused on accomplishing target peak power constraint, average power consumptions tended to be increasing in case of slack target peak power constraints.
Table 2 shows the result without using weight set compaction procedure.
Table 3 shows comparison between Table1 and Table2 (Table1 -Table2) in order to show the effectiveness of weight set compaction.In almost all cases, the required number of weight set is reduced.This will contribute to reduction of BIST circuit.Table 2. Experimental results without using weight set compaction.Table 3.Comparison between Table1 and Table2 ( Table1 -Table2).

Conclusion
This paper has proposed a multiple weight set weighted random BIST scheme with taking into account peak power constraint on scan testing and with performing weight set compaction.Experimental results showed that effective weight sets within peak scan capture power constraint could be obtained by proposed method.

Fig. 1 .
Fig. 1. Outline of power consumption between two consecutive test patterns.